Amaury Nève

According to our database1, Amaury Nève authored at least 6 papers between 1999 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Power-delay product minimization in high-performance 64-bit carry-select adders.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.
Proceedings of the Integrated Circuit and System Design, 2004

2003
SOI Technology for Future High-Performance Smart Cards.
IEEE Micro, 2003

2002
Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001
Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.
Proceedings of the SOC Design Methodologies, 2001

1999
Feasibility of the Smart Card in Silicon-On-Insulator (SOI) Technology.
Proceedings of the 1st Workshop on Smartcard Technology, 1999


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