Denis Flandre

According to our database1, Denis Flandre authored at least 97 papers between 1999 and 2021.

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A Wearable Low-Power Sensing Platform for Environmental and Health Monitoring: The Convergence Project.
Sensors, 2021

A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform.
IEEE J. Solid State Circuits, 2021

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.
IEEE J. Solid State Circuits, 2021

Performances Evaluation of On-Chip Large-Size-Tapped Transformer for MEMS Applications.
IEEE Trans. Instrum. Meas., 2020

Learning with Physical Noise or Errors.
IEEE Trans. Dependable Secur. Comput., 2020

Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors.
IEEE J. Solid State Circuits, 2019

A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs.
Integr., 2019

A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer.
Integr., 2019

Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA.
Proceedings of the 16th International Conference on Synthesis, 2019

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks.
IEEE Trans. Ind. Electron., 2018

Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Let's make it Noisy: A Simulation Methodology for adding Intrinsic Physical Noise to Cryptographic Designs.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

A Transient Noise Analysis of Secured Dual-Rail Based Logic Style.
Proceedings of the 2018 New Generation of CAS, 2018

Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Demonstrating an LPPN Processor.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

Multiple-Wavelength Detection in SOI Lateral PIN Diodes With Backside Reflectors.
IEEE Trans. Ind. Electron., 2017

Back-gate bias effect on UTBB-FDSOI non-linearity performance.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

A 16×16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell.
IEEE Trans. Biomed. Circuits Syst., 2016

Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load.
IEEE J. Solid State Circuits, 2016

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors.
IET Circuits Devices Syst., 2016

Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Automated design of a 13.56 MHz corner-robust efficient differential drive rectifier for 10 μA load.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Diamond layout style impact on SOI MOSFET in high temperature environment.
Microelectron. Reliab., 2015

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs.
IEEE J. Solid State Circuits, 2015

A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization.
J. Low Power Electron., 2015

Analysis and optimization for dynamic read stability in 28nm SRAM bitcells.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Wide band study of silicon-on-insulator photodiodes on suspended micro-hotplates platforms.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

A 0.48mm<sup>2</sup> 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage.
Proceedings of the ESSCIRC Conference 2015, 2015

A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Self-Oscillating System to Measure the Conductivity and the Permittivity of Liquids within a Single Triangular Signal.
J. Sensors, 2014

Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations.
J. Cryptogr. Eng., 2014

Variability of UTBB MOSFET analog figures of merit in wide frequency range.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference.
Sensors, 2013

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs.
Microelectron. Reliab., 2013

SleepWalker: A 25-MHz 0.4-V Sub-mm<sup>2</sup> 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.
IEEE J. Solid State Circuits, 2013

Validation of a Novel ultra-thin silicon Strip Detector for Hadron Therapy beam Monitoring.
J. Circuits Syst. Comput., 2013

Characterization of ultra-thin silicon strip detectors for hadrontherapy beam monitoring.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets.
Proceedings of the European Solid-State Device Research Conference, 2013

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs.
Microelectron. Reliab., 2012

Pushing Adaptive Voltage Scaling Fully on Chip.
J. Low Power Electron., 2012

Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology.
J. Low Power Electron., 2012

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer.
Microelectron. Reliab., 2011

Characterization and modelling of single event transients in LDMOS-SOI FETs.
Microelectron. Reliab., 2011

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptogr. Eng., 2011

Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices.
Proceedings of the Advances in Cryptology - EUROCRYPT 2011, 2011

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels.
ACM Trans. Design Autom. Electr. Syst., 2010

ULPFA: A New Efficient Design of a Power-Aware Full Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs.
Microelectron. Reliab., 2010

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Interests and Limitations of Technology Scaling for Subthreshold Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation.
Microelectron. J., 2008

Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Impact of Technology Scaling on Digital Subthreshold Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Analysis and minimization of practical energy in 45nm subthreshold logic circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
J. Multiple Valued Log. Soft Comput., 2007

Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs.
Microelectron. J., 2007

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode.
IEEE J. Solid State Circuits, 2007

Dynamic differential self-timed logic families for robust and low-power security ICs.
Integr., 2007

A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications.
Microelectron. J., 2006

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks.
Microelectron. J., 2006

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS.
Microelectron. J., 2006

Ultra-low power flip-flops for MTCMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power-delay product minimization in high-performance 64-bit carry-select adders.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.
Proceedings of the Integrated Circuit and System Design, 2004

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si: H photodiode.
Microelectron. Reliab., 2003

SOI Technology for Future High-Performance Smart Cards.
IEEE Micro, 2003

Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications.
IEEE Trans. Ind. Electron., 2001

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.
Proceedings of the SOC Design Methodologies, 2001

IF MEMS filters for mobile communication.
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001

Characterization, Simulation and Modeling of PLL under Irradiation Using HDL-A.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

Feasibility of the Smart Card in Silicon-On-Insulator (SOI) Technology.
Proceedings of the 1st Workshop on Smartcard Technology, 1999