Amit Golander

According to our database, Amit Golander authored at least 15 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Near-Memory Processing Offload to Remote (Persistent) Memory.

Roei Kisous, Amit Golander, Yigal Korman, Tim Gubner, Rune Humborstad, Manyi Lu

Proceedings of the 16th ACM International Conference on Systems and Storage, 2023

2022

pmAddr: a persistent memory centric computing architecture.

Amit Golander, Shai Taharlev, Yigal Korman

Proceedings of the SYSTOR '22: The 15th ACM International Systems and Storage Conference, Haifa, Israel, June 13, 2022

2018

Accelerating Unmodified Databases using Persistent Memory and Flash Storage Tiers.

Amit Golander, Netanel Katzburg, Omer Zilberberg

Proceedings of the 11th ACM International Systems and Storage Conference, 2018

2017

Persistent memory over fabric (PMoF).

Amit Golander, Sagi Manole, Yigal Korman

Proceedings of the 10th ACM International Systems and Storage Conference, 2017

2014

L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters.

Alexei Jolondz, Shlomo Weiss, Amit Golander

IEEE Trans. Very Large Scale Integr. Syst., 2014

Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators.

Sagi Manole, Amit Golander, Shlomo Weiss

IEEE Trans. Computers, 2014

2013

Leveraging predefined huffman dictionaries for high compression rate and ratio.

Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole

Proceedings of the 6th Annual International Systems and Storage Conference, 2013

High Compression Rate and Ratio Using Predefined Huffman Dictionaries.

Amit Golander, Shai Tahar, Lior Glass, Giora Biran, Sagi Manole

Proceedings of the 2013 Data Compression Conference, 2013

2011

A Cost-Efficient L1-L2 Multicore Interconnect: Performance, Power, and Area Considerations.

Amit Golander, Nadav Levison, Omer Heymann, Alexander Briskman, Mark J. Wolski, Eric F. Robinson

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009

Reexecution and Selective Reuse in Checkpoint Processors.

Amit Golander, Shlomo Weiss

Trans. High Perform. Embed. Archit. Compil., 2009

Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture.

Amit Golander, Shlomo Weiss, Ronny Ronen

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Checkpoint allocation and release.

Amit Golander, Shlomo Weiss

ACM Trans. Archit. Code Optim., 2009

2008

Hiding the misprediction penalty of a resource-efficient high-performance processor.

Amit Golander, Shlomo Weiss

ACM Trans. Archit. Code Optim., 2008

DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals.

Amit Golander, Shlomo Weiss, Ronny Ronen

IEEE Comput. Archit. Lett., 2008

Stateful hardware decompression in networking environment.

Hao Yu, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass

Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008