Nadav Levison

According to our database1, Nadav Levison authored at least 5 papers between 2009 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2011
A Cost-Efficient L1-L2 Multicore Interconnect: Performance, Power, and Area Considerations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation.
IET Comput. Digit. Tech., 2011

2010
Branch target buffer design for embedded processors.
Microprocess. Microsystems, 2010

Low power branch prediction for embedded application processors.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
History Index of Correct Computation for Fault-Tolerant Nano-Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2009


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