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Amitabha Sinha

According to our database1, Amitabha Sinha authored at least 22 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations.
[BibTeX]
[DOI]
Atri Sanyal
,
Amitabha Sinha
Int. J. Softw. Innov., 2022

2014
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation.
[BibTeX]
[DOI]
Atin Mukherjee
,
Amitabha Sinha
,
Debesh Choudhury
SIGARCH Comput. Archit. News, 2014

2013
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays.
[BibTeX]
[DOI]
Amitabha Sinha
,
Mitrava Sarkar
,
Soumojit Acharyya
,
Suranjan Chakraborty
SIGARCH Comput. Archit. News, 2013

Performance analysis of a FPGA based novel binary and DBNS multiplier.
[BibTeX]
[DOI]
Amrita Saha
,
Manideepa Mukherjee
,
Debanjana Datta
,
Sangita Saha
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2013

An integrated development platform of a reconfigurable radio processor for software defined radio.
[BibTeX]
[DOI]
Amrita Saha
,
Pijush Biswas
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2013

FPGA implementation of a novel DCT architecture reducing constant cosine terms.
[BibTeX]
[DOI]
Santanu Pal
,
Amitabha Sinha
,
Pijush Biswas
SIGARCH Comput. Archit. News, 2013

Design and simulation of MAC unit using combinational circuit and adder.
[BibTeX]
[DOI]
Subhashis Maitra
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2013

High efficiency MAC unit used in digital signal processing and elliptic curve cryptography.
[BibTeX]
[DOI]
Subhashis Maitra
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2013

High performance MAC unit for DSP and cryptographic applications.
[BibTeX]
[DOI]
Subhashis Maitra
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2013

Field Programmable DSP Arrays - A
[BibTeX]
[DOI]
Amitabha Sinha
,
Soumojit Acharyya
,
Suranjan Chakraborty
,
Mitrava Sarkar
CoRR, 2013

2012
A new algorithm for computing triple-base number system.
[BibTeX]
[DOI]
Subhashis Maitra
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2012

FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT.
[BibTeX]
[DOI]
Nishant Kumar Giri
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2012

"Floating point RNS": a new concept for designing the MAC unit of digital signal processor.
[BibTeX]
[DOI]
Aniruddha Ghosh
,
Satrughna Singha
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2012

A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system.
[BibTeX]
[DOI]
Aniruddha Ghosh
,
Satrughna Singha
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2012

Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System
[BibTeX]
[DOI]
Chaitali Biswas Dutta
,
Partha Garai
,
Amitabha Sinha
CoRR, 2012

A Scheme for Improving Bit Efficiency for Residue Number System.
[BibTeX]
[DOI]
Chaitali Biswas Dutta
,
Partha Garai
,
Amitabha Sinha
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012

2011
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique.
[BibTeX]
[DOI]
Satrughna Singha
,
Aniruddha Ghosh
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2011

High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA).
[BibTeX]
[DOI]
Malay Das
,
Amitabha Sinha
,
Nishant Kumar Giri
SIGARCH Comput. Archit. News, 2011

Conversion of binary to single-term triple base numbers for DSP applications.
[BibTeX]
[DOI]
Anindita Chakraborty
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2011

2010
A novel architecture for conversion of binary to single digit double base numbers.
[BibTeX]
[DOI]
Manideepa Mukherjee
,
Amitabha Sinha
SIGARCH Comput. Archit. News, 2010

A reconfigurable Digital Signal Processor using residue number system.
[BibTeX]
[DOI]
Sharbari Banerjee
,
Amitabha Sinha
Proceedings of the 10th International Conference on Information Sciences, 2010

2009
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio.
[BibTeX]
[DOI]
Amrita Saha
,
Amitabha Sinha
Proceedings of the 2009 International Conference on Education Technology and Computer, 2009


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