Amjad Hajjar

According to our database1, Amjad Hajjar authored at least 19 papers between 1991 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
Network traffic application identification based on message size analysis.
J. Netw. Comput. Appl., 2015

2014
A multilevel taxonomy and requirements for an optimal traffic-classification model.
Int. J. Netw. Manag., 2014

2013
Performance of OpenDPI in Identifying Sampled Network Traffic.
J. Networks, 2013

2011
Performance of OpenDPI to Identify Truncated Network Traffic.
Proceedings of the DCNET 2011 and OPTICS 2011, 2011

2004
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification.
J. Electron. Test., 2002

Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

An Accurate Coverage Forecasting Model for Behavioral Model Verification.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Stopping Criteria Comparison: Towards High Quality Behavioral Verification.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

High quality behavioral verification using statistical stopping criteria.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Achieving the Quality of Verification for Behavioral Models with Minimum Effort.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

On choosing test criteria for behavioral level hardware design verification.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

On statistical behavior of branch coverage in testing behavioral VHDL models.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

1999
VLSI Architecture for Real-Time Edge Linking.
IEEE Trans. Pattern Anal. Mach. Intell., 1999

Efficient Verification of Behavioral Models Using Sequential Sampling Technique.
Proceedings of the VLSI: Systems on a Chip, 1999

How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing.
Proceedings of the 4th IEEE International Symposium on High-Assurance Systems Engineering (HASE '99), 1999

1998
Fast Antirandom (FAR) Test Generation.
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998

1991
TAS: an accurate timing analyser for CMOS VLSI.
Proceedings of the conference on European design automation, 1991


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