Alain Greiner

According to our database, Alain Greiner authored at least 57 papers between 1988 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

IEEE J. Solid State Circuits, 2021

2020

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.

Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

Decoupling Translation Lookaside Buffer Coherence from Cache Coherence.

Hao Liu, Quentin L. Meunier, Alain Greiner

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures.

Mohamed Lamine Karaoui, Pierre-Yves Peneau, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2015

GECOS : Mécanisme de synchronisation passant à l'échelle à plusieurs lecteurs et un écrivain pour structures chaînées.

Mohamed Lamine Karaoui, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner

Tech. Sci. Informatiques, 2015

RWT: Suppressing Write-Through Cost When Coherence is Not Needed.

Hao Liu, Clement Devigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures.

Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context.

Eric Guthmuller, Ivan Miro Panades, Alain Greiner

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012

Adaptive Stackable 3D Cache Architecture for Manycores.

Eric Guthmuller, Ivan Miro Panades, Alain Greiner

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure.

Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs.

Joël Porquet, Alain Greiner, Christian Schwarz

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS.

François Pêcheux, Khouloud Zine el Abidine, Alain Greiner

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components.

Zhen Zhang, Alain Greiner, Mounir Benabdenbi

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations.

Aline Mello, Isaac Maia, Alain Greiner, François Pêcheux

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs.

Nicolas Pouillon, Alexandre Bécoulet, Aline Vieira de Mello, François Pêcheux, Alain Greiner

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Multi-compartment: A new architecture for secure co-hosting on SoC.

Joël Porquet, Christian Schwarz, Alain Greiner

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip.

Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius

Proceedings of the Forum on specification and Design Languages, 2009

2008

Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures.

Abbas Sheibanyrad, Alain Greiner

Integr., 2008

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures.

Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades

IEEE Des. Test Comput., 2008

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.

Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.

Zhen Zhang, Alain Greiner, Sami Taktak

Proceedings of the 45th Design Automation Conference, 2008

2007

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN.

Hervé Charlery, Adrijean Andriahantenaina, Alain Greiner

Comput. Electr. Eng., 2007

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.

Matthieu Tuna, Mounir Benabdenbi, Alain Greiner

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures.

Ivan Miro Panades, Alain Greiner

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture.

Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures.

Abbas Sheibanyrad, Alain Greiner

Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation.

Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications.

Etienne Faure, Alain Greiner, Daniela Genius

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.

Abbas Sheibanyrad, Alain Greiner

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach.

Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.

Frédéric Pétrot, Alain Greiner, Pascal Gomez

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles.

Emmanuel Viaud, François Pêcheux, Alain Greiner

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Estimating Energy Consumption for an MPSoC Architectural Exploration.

Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser

Proceedings of the Architecture of Computing Systems, 2006

2004

A language to desing generators of analog functions (poster).

Marie-Minerve Louërat, Tuong P. Nguyen, Vincent Bourguet, Laurent de Lamarre, Alain Greiner

Proceedings of the Forum on specification and Design Languages, 2004

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.

Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna

Proceedings of the 2004 Design, 2004

2003

Micro-Network for SoC: Implementation of a 32-Port SPIN network.

Adrijean Andriahantenaina, Alain Greiner

Proceedings of the 2003 Design, 2003

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network.

Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, César Albenes Zeferino

Proceedings of the 2003 Design, 2003

2001

Protocol and Performance Analysis of the MPC Parallel Computer.

Jean Lou Desbarbieux, Olivier Glück, Amal Zerrouki, Alexandre Fenyo, Alain Greiner, Franck Wajsbürt, Cyril Spasevski, Fabrício Silva, E. Dreyfus

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Analog design for reuse - case study: very low-voltage sigma-delta modulator.

Mohamed Dessouky, Andreas Kaiser, Marie-Minerve Louërat, Alain Greiner

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

A Generic Architecture for On-Chip Packet-Switched Interconnections.

Pierre Guerrier, Alain Greiner

Proceedings of the 2000 Design, 2000

1997

Cycle precise core based hardware/software system simulation with predictable event propagation.

Frédéric Pétrot, Denis Hommais, Alain Greiner

Proceedings of the 23rd EUROMICRO Conference '97, 1997

A Simulation Environment for Core Based Embedded Systems.

Frédéric Pétrot, Denis Hommais, Alain Greiner

Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

1996

A portable clock multiplier generator using digital CMOS standard cells.

Michel Combes, Karim Dioury, Alain Greiner

IEEE J. Solid State Circuits, 1996

1995

A High Performance Modular Embedded ROM Architecture.

Marcello Duhalde, Alain Greiner, Frédéric Pétrot

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

RAPID-2, An Object-Oriented Associative Memory Applicable to Genome Data Processing.

Denis Archambaud, Pascal Faudemay, Alain Greiner

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.

Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Using C to write portable CMOS VLSI module generators.

Alain Greiner, Frédéric Pétrot

Proceedings of the Proceedings EURO-DAC'94, 1994

Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library.

Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Multilevel Logic Synthesis of Very High Complexity Circuits.

Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Multilevel logic optimization of very high complexity circuits.

Luc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary

Proceedings of the Proceedings EURO-DAC'94, 1994

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking.

Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan

Proceedings of the Proceedings 27th Annual Simulation Symposium, 1994

1992

FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout.

Lotfi Ben Ammar, Alain Greiner

Proceedings of the Synthesis for Control Dominated Circuits, 1992

DESB, a functional abstractor for CMOS VLSI circuits.

Marc Laurentin, Alain Greiner, Roland Marbot

Proceedings of the conference on European design automation, 1992

1991

TAS: an accurate timing analyser for CMOS VLSI.

Amjad Hajjar, Alain Greiner, Roland Marbot, Payam Kiani

Proceedings of the conference on European design automation, 1991

GENVIEW: a portable source-level debugger for macrocell generators.

A. Compan, Alain Greiner, François Pêcheux, Frédéric Pétrot

Proceedings of the conference on European design automation, 1991

1988

NOISY: an electrical noise checker for ULSI.

F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988