Ana Isabela Araújo Cunha

Orcid: 0000-0003-3955-3430

According to our database1, Ana Isabela Araújo Cunha authored at least 32 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Improving Output Voltage Swing in Cascode Current Mirrors.
Circuits Syst. Signal Process., June, 2023

2022
Application of improved ACM model to the design by hand of CMOS analog circuits.
Microelectron. J., 2022

A Graphical Interface Learning Tool for Image Processing Through Analog CNN.
Circuits Syst. Signal Process., 2022

2020
A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Proportional Source Transconductances Integrator for CMOS Analog Filtering with Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Improvements on the Design of the Low Saturation Onset Transistor.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
CMOS analog four-quadrant multiplier free of voltage reference generators.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

A Very Compact CMOS Analog Multiplier for Application in CNN Synapses.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

CNN Learning for Image Processing: Center of Mass versus Genetic Algorithms.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
CMOS analog filter design using the Proportional Source Transconductances Integrator.
Microelectron. J., 2018

2017
Improvements to a compact MOSFET model for design by hand.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Improving a MOSFET model for design by hand.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
Distortion analysis of integrated analog multipliers: DC versus AC approaches.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
Image filtering in a CMOS analog CNN.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2013
An experiment set-up for analysis of lateralization judgments of binaural stimuli.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

2011
Optimized sizing of analog circuits using the interior-point method for nonconvex nonlinear functions under MATLAB.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
A new architecture of companding integrator for CMOS current-mode analog filters.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
CMOS multiplier based on the relationship between drain current and inversion charge.
IET Circuits Devices Syst., 2009

ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
Systematic methodology for the design of Seevinck's CMOS log-domain integrators.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007
The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A general domain CMOS companding integrator.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2005
On the adequate transistor modeling for optimal design of CMOS OTA.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

CMOS analog current-mode multiplier based on the advanced compact MOSFET model.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Application of ACM model to the design of CMOS OTA through a graphical approach.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
CMOS OTA Sizing Using ACM Model in a Graphical Approach.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

1998
An MOS transistor model for analog circuit design.
IEEE J. Solid State Circuits, 1998

A single-piece charge-based model for the output conductance of MOS transistors.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A compact charge-based MOSFET model for circuit simulation.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995
An Explicit MOSFET Model for Analog Circuit Simulation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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