Anawin Opasatian

Orcid: 0009-0006-0547-4020

According to our database¹, Anawin Opasatian authored at least 4 papers between 2023 and 2026.

Collaborative distances:

Timeline

Book In proceedings Article PhD thesis Dataset Other

2026

Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption.

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., February, 2026

2025

Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier.

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., January, 2025

2023

Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor.

[DOI]

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023

High-Performance BLS12-381 Pairing Engine on FPGA.

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023