André Seffrin
According to our database1,
André Seffrin
authored at least 11 papers
between 2009 and 2012.
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Bibliography
2012
A Process-Algebraic Approach to Security-Aware Scheduling of Dynamic Partial Reconfiguration on FPGA Devices.
PhD thesis, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis.
Proceedings of the IEEE 10th International Conference on Trust, 2011
Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability.
Proceedings of the International Conference on Field-Programmable Technology, 2010
Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
2009
DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code.
Proceedings of the Forum on specification and Design Languages, 2009