Andrea Pierazzi

According to our database1, Andrea Pierazzi authored at least 4 papers between 1998 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2001
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS.
IEEE J. Solid State Circuits, 2001

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2001

Band-gap references for near 1-V operation in standard CMOS technology.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1998
Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998


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