Andreas Lööw

According to our database1, Andreas Lööw authored at least 8 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor.
Proceedings of the Formal Methods in Computer-Aided Design, 2023

Exact Separation Logic: Towards Bridging the Gap Between Verification and Bug-Finding.
Proceedings of the 37th European Conference on Object-Oriented Programming, 2023

2022
Exact Separation Logic.
CoRR, 2022

A small, but important, concurrency problem in Verilog's semantics? (Work in progress).
Proceedings of the 20th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2022

Reconciling Verified-Circuit Development and Verilog Development.
Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022

2021
Lutsig: a verified Verilog compiler for verified circuit development.
Proceedings of the CPP '21: 10th ACM SIGPLAN International Conference on Certified Programs and Proofs, 2021

2019
Verified compilation on a verified processor.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

A proof-producing translator for verilog development in HOL.
Proceedings of the 7th International Workshop on Formal Methods in Software Engineering, 2019


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