Aniseh Dorostkar

Orcid: 0000-0003-2596-0721

According to our database1, Aniseh Dorostkar authored at least 4 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2025
An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators.
IEEE Trans. Reliab., March, 2025

2018
A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age.
EURASIP J. Embed. Syst., 2018

Optimization-based reconfigurable approach for low-power 3D chip-multiprocessors.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors.
Proceedings of the Euromicro Conference on Digital System Design, 2017


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