Anying Jiang
Orcid: 0009-0005-9804-8073
According to our database1,
Anying Jiang
authored at least 3 papers
between 2024 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024