Anying Jiang

Orcid: 0009-0005-9804-8073

According to our database1, Anying Jiang authored at least 3 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024


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