Arash Azizi Mazreah

According to our database, Arash Azizi Mazreah authored at least 7 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style.

Vahid Foroutan, MohammadReza Taheri, Keivan Navi, Arash Azizi Mazreah

Integr., 2014

2013

Low-leakage soft error tolerant port-less configuration memory cells for FPGAs.

Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani

Integr., 2013

2012

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications.

Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani

Microelectron. J., 2012

2011

New configuration memory cells for FPGA in nano-scaled CMOS technology.

Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani

Microelectron. J., 2011

2009

A High Density and Low Power Cache Based on Novel SRAM Cell.

Arash Azizi Mazreah, Mohammad Taghi Manzuri, Ali Mehrparvar

J. Comput., 2009

A low power and high density cache memory based on novel SRAM cell.

Arash Azizi Mazreah, Mohammad Noorollahi Romani, Mohammad Taghi Manzuri, Ali Mehrparvar

IEICE Electron. Express, 2009

2008

A Low Power SRAM Based on Five Transistors Cell.

Arash Azizi Mazreah, Mohammad Taghi Manzuri Shalmani

Proceedings of the Advances in Computer Science and Engineering, 2008