Keivan Navi

According to our database1, Keivan Navi authored at least 139 papers between 1993 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Novel efficient full adder and full subtractor designs in quantum cellular automata.
J. Supercomput., 2020

A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry.
Microprocess. Microsystems, 2020

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source.
IET Comput. Digit. Tech., 2020

High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4: 2 compressor design in CNFET technology.
IET Circuits Devices Syst., 2020

HQCA-WSN: High-quality clustering algorithm and optimal cluster head selection using fuzzy logic in wireless sensor networks.
Fuzzy Sets Syst., 2020

Novel Optimum Parity-Preserving Reversible Multiplier Circuits.
Circuits Syst. Signal Process., 2020

Optimized Quantum Circuit Partitioning.
CoRR, 2020

Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata.
Comput. Electr. Eng., 2020

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors.
Comput. Electr. Eng., 2020

2019
Design and analysis of efficient QCA reversible adders.
J. Supercomput., 2019

Improving rule-based classification using Harmony Search.
PeerJ Comput. Sci., 2019

Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology.
Microelectron. J., 2019

Partial product generation for unbalanced ternary signed multiplication.
Int. J. High Perform. Syst. Archit., 2019

Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019

Optimal selection of ensemble classifiers using particle swarm optimization and diversity measures.
Intell. Decis. Technol., 2019

Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter.
Circuits Syst. Signal Process., 2019

2018
Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs.
IEEE Trans. Fuzzy Syst., 2018

Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata.
J. Low Power Electron., 2018

Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate.
J. Circuits Syst. Comput., 2018

A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates.
Integr., 2018

An energy and area efficient 4: 2 compressor based on FinFETs.
Integr., 2018

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic.
Circuits Syst. Signal Process., 2018

2017
CAST-WSN: The Presentation of New Clustering Algorithm Based on Steiner Tree and C-Means Algorithm Improvement in Wireless Sensor Networks.
Wirel. Pers. Commun., 2017

A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs.
J. Multiple Valued Log. Soft Comput., 2017

Quantum-dot cellular automata circuits with reduced external fixed inputs.
Microprocess. Microsystems, 2017

Towards ultra-efficient QCA reversible circuits.
Microprocess. Microsystems, 2017

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors.
Frontiers Inf. Technol. Electron. Eng., 2017

Towards Approximate Computing with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2017

High-performance ternary operators for scrambling.
Integr., 2017

Method for designing ternary adder cells based on CNFETs.
IET Circuits Devices Syst., 2017

A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates.
IET Circuits Devices Syst., 2017

High Performance CNFET-based Ternary Full Adders.
CoRR, 2017

2016
Ternary cyclic redundancy check by a new hardware-friendly ternary operator.
Microelectron. J., 2016

CNFET-based approximate ternary adders for energy-efficient image processing applications.
Microprocess. Microsystems, 2016

Design and analysis of carbon nanotube FET based quaternary full adders.
Frontiers Inf. Technol. Electron. Eng., 2016

An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs.
J. Low Power Electron., 2016

Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells.
J. Comput. Sci., 2016

Rotation-Based Design and Synthesis of Quantum Circuits.
J. Circuits Syst. Comput., 2016

New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters.
IEICE Trans. Electron., 2016

A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs.
Circuits Syst. Signal Process., 2016

Design of quaternary 4-2 and 5-2 compressors for nanotechnology.
Comput. Electr. Eng., 2016

Area-delay-power-aware adder placement method for RNS reverse converter design.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach.
Microelectron. J., 2015

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata.
Microelectron. J., 2015

Designing quantum-dot cellular automata counters with energy consumption analysis.
Microprocess. Microsystems, 2015

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder.
J. Low Power Electron., 2015

New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources.
J. Electr. Comput. Eng., 2015

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015

Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata.
Inf. Sci., 2015

New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources.
Int. J. High Perform. Syst. Archit., 2015

New fully single layer QCA full-adder cell based on feedback model.
Int. J. High Perform. Syst. Archit., 2015

High-performance ternary logic gates for nanoelectronics.
Int. J. High Perform. Syst. Archit., 2015

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic.
IET Circuits Devices Syst., 2015

Designing Nanoelectronic-Compatible 8-bit Square Root Circuit by Quantum-Dot Cellular Automata.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014
High-Efficient Circuits for Ternary Addition.
VLSI Design, 2014

Synthesis and Optimization by Quantum Circuit Description Language.
Trans. Comput. Sci., 2014

Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2014

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata.
J. Comput. Syst. Sci., 2014

A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors.
J. Circuits Syst. Comput., 2014

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style.
Integr., 2014

On the Design of RNS Bases for Modular Multiplication.
Int. J. Netw. Secur., 2014

Optimized Adder Cells for Ternary Ripple-Carry Addition.
IEICE Trans. Inf. Syst., 2014

Efficient Reverse Converters for 4-Moduli Sets {2<sup>2n-1</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1, 2<sup>n</sup>-1} and {2<sup>2n-1</sup>, 2<sup>2n-1</sup>-1, 2<sup>n</sup>+1, 2<sup>n</sup>-1} Based on CRTs Algorithm.
Circuits Syst. Signal Process., 2014

A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits.
Comput. Syst. Sci. Eng., 2014

Designing high-speed, low-power full adder cells based on carbon nanotube technology.
CoRR, 2014

2013
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Multi-output majority gate-based design optimization by using evolutionary algorithm.
Swarm Evol. Comput., 2013

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic.
Microelectron. J., 2013

Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors.
Int. J. High Perform. Syst. Archit., 2013

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.
IET Comput. Digit. Tech., 2013

Coplanar wire crossing in quantum cellular automata using a ternary cell.
IET Circuits Devices Syst., 2013

New CNTFET-Based Arithmetic Cells with Weighted Inputs for High Performance Energy Efficient Applications.
IEICE Trans. Electron., 2013

An efficient cntfet-based 7-input minority gate
CoRR, 2013

Dramatically Low-Transistor-Count High-Speed Ternary Adders.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

2012
Ultra-area-efficient reversible multiplier.
Microelectron. J., 2012

New robust QCA D flip flop and memory structures.
Microelectron. J., 2012

An Energy-Efficient Full Adder Cell Using CNFET Technology.
IEICE Trans. Electron., 2012

A new SPICE model for organic molecular transistors and a novel hybrid architecture.
IEICE Electron. Express, 2012

Efficient RNS to binary converters for the new 4-moduli set {2<sup><i>n</i></sup>, 2<sup><i>n</i>+1</sup>-1, 2<sup><i>n</i></sup>-1, 2<sup><i>n</i>-1</sup>-1}.
IEICE Electron. Express, 2012

Design and Evaluation of CNFET-Based Quaternary Circuits.
Circuits Syst. Signal Process., 2012

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology.
Circuits Syst. Signal Process., 2012

A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders
CoRR, 2012

A New Full Adder Cell for Molecular Electronics
CoRR, 2012

A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular Automata.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011
How to Teach Residue Number System to Computer Scientists and Engineers.
IEEE Trans. Educ., 2011

Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata.
Microelectron. J., 2011

Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology.
Microelectron. J., 2011

A New Switched opamp Approach for Improving the Operation of Auto-Reset Switched-capacitor Filters.
J. Circuits Syst. Comput., 2011

A New Robust and High-Performance Hybrid Full Adder Cell.
J. Circuits Syst. Comput., 2011

High-speed full adder based on minority function and bridge style for nanoscale.
Integr., 2011

Design of energy-efficient and robust ternary circuits for nanotechnology.
IET Circuits Devices Syst., 2011

A General Reverse Converter Architecture with Low Complexity and High Performance.
IEICE Trans. Inf. Syst., 2011

A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders.
Fuzzy Sets Syst., 2011

Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes.
Comput. Electr. Eng., 2011

2010
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits.
VLSI Design, 2010

Efficient Reverse Converter Designs for the New 4-Moduli Sets 2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup> +1, 2<sup>2n + 1</sup>-1 and 2<sup>n</sup> -1, 2<sup>n</sup> +1, 2<sup>2n</sup>, 2<sup>2n</sup> +1 Based on New CRTs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A new quantum-dot cellular automata full-adder.
Microelectron. J., 2010

Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates.
IEICE Trans. Electron., 2010

High speed reverse converter for new five-moduli set {2<sup>n</sup>, 2<sup>2n+1</sup>-1, 2<sup>n/2</sup>-1, 2<sup>n/2</sup>+1, 2<sup>n</sup>+1}.
IEICE Electron. Express, 2010

A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A new four-modulus RNS to binary converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Redundant Multi-Level one-hot Residue Number System based error correction codes.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
Arithmetic Circuits of Redundant SUT-RNS.
IEEE Trans. Instrum. Meas., 2009

Two new low-power Full Adders based on majority-not gates.
Microelectron. J., 2009

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter.
Microelectron. J., 2009

A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic.
J. Low Power Electron., 2009

Optimized Reversible Multiplier Circuit.
J. Circuits Syst. Comput., 2009

Two New Low-Power and High-Performance Full Adders.
J. Comput., 2009

A novel low-power full-adder cell for low voltage.
Integr., 2009

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>+1</sup> -1} and {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>-1</sup> -1}.
IEICE Trans. Inf. Syst., 2009

A new algorithm for determining all possible symmetric hybrid redundant numbers.
IEICE Electron. Express, 2009

Two novel ultra high speed carbon nanotube Full-Adder cells.
IEICE Electron. Express, 2009

An energy efficient full adder cell for low voltage.
IEICE Electron. Express, 2009

A new five-moduli set for efficient hardware implementation of the reverse converter.
IEICE Electron. Express, 2009

On the design of low power 1-bit full adder cell.
IEICE Electron. Express, 2009

Efficient Carbon Nanotube Galois Field Circuit Design.
IEICE Electron. Express, 2009

A High Dynamic Range 3-Moduli-Set with Efficient Reverse Converter
CoRR, 2009

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008
Parallel Lagrange interpolation on <i>k</i> -ary <i>n</i> -cubes with maximum channel utilization.
J. Supercomput., 2008

An efficient architecture for designing reverse converters based on a general three-moduli set.
J. Syst. Archit., 2008

Reliable and Secure Chip Level Communication by residue number System Code.
Trans. SDPS, 2008

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell.
J. Comput., 2008

Ultra high speed Full Adders.
IEICE Electron. Express, 2008

An improved reverse converter for the moduli set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1}.
IEICE Electron. Express, 2008

A new high dynamic range moduli set with efficient reverse converter.
Comput. Math. Appl., 2008

Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Performance evaluation of In-Circuit Testing on QCA based circuits.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

2007
A Novel CMOS Full Adder.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Performance Modeling of Wormhole Hypermeshes Under Hotspot Traffic.
Proceedings of the Computer Science, 2007

A New Design for 7: 2 Compressors.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Using Car Semi-Active Suspension Systems To Decrease Undesirable Effects Of Road Excitations On Human Health.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006

Reducing Harmful Effects Of Road Excitations On Human Health By Designing Car Active Suspension Systems.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006

2005
Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution.
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005

1995
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994
Performance of CMOS Current Mode Full Adders.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

CML Current Mode Full Adders for 2.5-V Power Supply.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993
A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993


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