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Ardhendu Sarkar

Orcid: 0000-0002-4555-3026

According to our database1, Ardhendu Sarkar authored at least 4 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2025
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA.
[BibTeX]
[DOI]
Ardhendu Sarkar
,
Sriparna Mandal
,
Surajeet Ghosh
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment.
[BibTeX]
[DOI]
Ardhendu Sarkar
,
Surajeet Ghosh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

2020
An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment.
[BibTeX]
[DOI]
Ardhendu Sarkar
,
Som Banerjee
,
Surajeet Ghosh
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU.
[BibTeX]
[DOI]
Ardhendu Sarkar
,
Kinjal Ray
,
Debaroti Chowdhury
,
Kishan Sahu
,
Solanki Kundu
,
Surajeet Ghosh
Proceedings of the TENCON 2019, 2019


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