Surajeet Ghosh

According to our database, Surajeet Ghosh authored at least 15 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation.

Sriparna Mandal, Surajeet Ghosh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

2025

CB-ED-RPL: Coordinator-Based Energy-Efficient Dynamic RPL for IoT Networks.

Surajeet Ghosh

Wirel. Pers. Commun., December, 2025

Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA.

Ardhendu Sarkar, Sriparna Mandal, Surajeet Ghosh

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024

Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment.

Ardhendu Sarkar, Surajeet Ghosh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

2023

${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform.

Surajeet Ghosh, Sanchita Saha Ray

IEEE Trans. Computers, July, 2023

k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting.

Sanchita Saha Ray, Surajeet Ghosh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

2022

Worst Case O(N) Comparison-Free Hardware Sorting Engine.

Sanchita Saha Ray, Dulal Adak, Surajeet Ghosh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing.

Sanchita Saha Ray, Surajeet Ghosh, Bhaskar Sardar

IEEE Trans. Computers, 2022

CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism.

Surajeet Ghosh, Anirban Chand

Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2022

2020

An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment.

Ardhendu Sarkar, Som Banerjee, Surajeet Ghosh

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU.

Ardhendu Sarkar, Kinjal Ray, Debaroti Chowdhury, Kishan Sahu, Solanki Kundu, Surajeet Ghosh

Proceedings of the TENCON 2019, 2019

A Comparison-free Hardware Sorting Engine.

Surajeet Ghosh, Shaon Dasgupta, Sanchita Saha Ray

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing.

Sanchita Saha Ray, Sonal Singh, Chandrayan Sengupta, Surajeet Ghosh, Bhaskar Sardar

Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018

2016

An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup.

Sanchita Saha Ray, Surajeet Ghosh, Bhaskar Sardar

Photonic Netw. Commun., 2016

2015

SRAM based longest prefix matching approach for multigigabit IP processing.

Sanchita Saha Ray, Surajeet Ghosh, Bhaskar Sardar

Proceedings of the 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2015