Surajeet Ghosh

Orcid: 0000-0003-1428-9530

According to our database1, Surajeet Ghosh authored at least 11 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform.
IEEE Trans. Computers, July, 2023

k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

2022
Worst Case O(N) Comparison-Free Hardware Sorting Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing.
IEEE Trans. Computers, 2022

CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2022

2020
An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU.
Proceedings of the TENCON 2019, 2019

A Comparison-free Hardware Sorting Engine.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018

2016
An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup.
Photonic Netw. Commun., 2016

2015
SRAM based longest prefix matching approach for multigigabit IP processing.
Proceedings of the 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2015


  Loading...