Arghavan Mohammadhassani

Orcid: 0009-0007-3782-3392

According to our database1, Arghavan Mohammadhassani authored at least 11 papers between 2019 and 2025.

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Bibliography

2025
Improving Scalability of NoC-Based Neuromorphic Hardware with Compressed AER (C-AER) Protocol.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Digital Neuromorphic Architecture for Unsupervised Shortest Path Computation on Real-World Graphs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Framework for Automatic Synthesis of Neuromorphic Architectures with Heterogeneous Integration of CMOS and Memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture.
CoRR, 2024

A Fully-Configurable Digital Spiking Neuromorphic Hardware Design with Variable Quantization and Mixed Precision.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

CMOS-Memristor Hybrid Design of A Neuromorphic Crossbar Array with Integrated Inference and Training.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024


Towards Biology-Inspired Fault Tolerance of Neuromorphic Hardware for Space Applications.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

QUANTISENC++: A Fully-Configurable Many-Core Neuromorphic Hardware.
Proceedings of the 58th Asilomar Conference on Signals, 2024

2023
Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM.
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

2019
Enhanced graph processing in PIM accelerators with improved queue management.
Microelectron. J., 2019


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