Masoud Dehyadegari

According to our database, Masoud Dehyadegari authored at least 19 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers.

Alireza Dehghanpour, Javad Khodamoradi Kordestani, Masoud Dehyadegari

Neural Process. Lett., December, 2023

2021

Linear-time error calculation for approximate adders.

Morteza Rezaalipour, Masoud Dehyadegari

Comput. Electr. Eng., 2021

G-Arrays: Geometric Arrays for Efficient Point Cloud Processing.

Hoda Roodaki, Masoud Dehyadegari, Mahdi Nazm Bojnordi

Proceedings of the IEEE International Conference on Acoustics, 2021

Memristive Data Ranking.

Ananth Krishna Prasad, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

AxMAP: Making Approximate Adders Aware of Input Patterns.

Morteza Rezaalipour, Mohammad Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi

IEEE Trans. Computers, 2020

2019

Designing energy-efficient imprecise adders with multi-bit approximation.

Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari

Microelectron. J., 2019

IDrAx: A tool-chain for designing efficient approximate adders.

Morteza Rezaalipour, Mohammad Rezaalipour, Sarvenaz Tajasob, Masoud Dehyadegari

Microelectron. J., 2019

Enhanced graph processing in PIM accelerators with improved queue management.

Mohammad Amin Mosayebi, Arghavan Mohammad Hasani, Masoud Dehyadegari

Microelectron. J., 2019

2018

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks.

Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2015

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators.

Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Siamak Mohammadi, Nasser Yazdani, Luca Benini

IEEE Trans. Computers, 2015

2013

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip.

Masoumeh Ebrahimi, Hannu Tenhunen, Masoud Dehyadegari

J. Syst. Archit., 2013

Distributed fair DRAM scheduling in network-on-chips architecture.

Masoud Dehyadegari, Siamak Mohammadi, Nasser Yazdani

J. Syst. Archit., 2013

2012

A tightly-coupled multi-core cluster with shared-memory HW accelerators.

Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.

Masoud Dehyadegari, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Siamak Mohammadi

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Real-time embedded emotional controller.

Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi

Neural Comput. Appl., 2010

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization.

Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Emotion on FPGA: Model driven approach.

Mohammad Reza Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi

Expert Syst. Appl., 2009

2006

A New Protocol Stack Model for Network on Chip.

Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

2005

Power and delay optimization for network on chip.

Mohsen Nickray, Masoud Dehyadegari, Ali Afzali-Kusha

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005