Ariel L. Pola

According to our database, Ariel L. Pola authored at least 6 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2017

Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems.

Benjamín T. Reyes, Raul M. Sanchez, Ariel L. Pola, Mario R. Hueda

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016

Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems.

Genaro Bergero, Damián A. Morero, Ariel L. Pola, Mario A. Castrillon, Mario R. Hueda

Proceedings of the 8th IEEE Latin-American Conference on Communications, 2016

An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems.

Raul M. Sanchez, Benjamín T. Reyes, Ariel L. Pola, Mario Rafael Hueda

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2013

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels.

Ariel L. Pola, Juan E. Cousseau, Oscar E. Agazzi, Mario Rafael Hueda

J. Electr. Comput. Eng., 2013

Efficient decision feedforward equalizer with parallelizable architecture.

Ariel L. Pola, Juan E. Cousseau, Oscar E. Agazzi, Mario Rafael Hueda

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011

A new low complexity iterative equalization architecture for high-speed receivers on highly dispersive channels: Decision feedforward equalizer (DFFE).

Ariel L. Pola, Diego E. Crivelli, Juan E. Cousseau, Oscar E. Agazzi, Mario Rafael Hueda

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011