Arish S

According to our database, Arish S authored at least 4 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm.

Arish S, R. K. Sharma

CoRR, 2019

Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications.

Arish S, R. K. Sharma

CoRR, 2019

Optimization of Convolutional Neural Networks on Resource Constrained Devices.

Arish S, Sharad Sinha, Smitha K. G.

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2017

Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.

Arish S, R. K. Sharma

Circuits Syst. Signal Process., 2017