According to our database1, Arish S authored at least 4 papers between 2017 and 2019.
Legend:Book In proceedings Article PhD thesis Other
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm.
Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
Circuits Syst. Signal Process., 2017