Arish S

According to our database1, Arish S authored at least 4 papers between 2017 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm.
CoRR, 2019

Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications.
CoRR, 2019

Optimization of Convolutional Neural Networks on Resource Constrained Devices.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2017
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
Circuits Syst. Signal Process., 2017


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