Arun Janarthanan

According to our database, Arun Janarthanan authored at least 2 papers between 2007 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks.

Arun Janarthanan, Karen A. Tomko

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems.

Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007