Arun Palaniappan

According to our database, Arun Palaniappan authored at least 2 papers between 2010 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures.

Arun Palaniappan, Samuel Palermo

IEEE Trans. Very Large Scale Integr. Syst., 2013

2010

Power Efficiency Comparisons of Interchip Optical Interconnect Architectures.

Arun Palaniappan, Samuel Palermo

IEEE Trans. Circuits Syst. II Express Briefs, 2010