Samuel Palermo

According to our database1, Samuel Palermo authored at least 54 papers between 2007 and 2019.

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Bibliography

2019
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
J. Solid-State Circuits, 2019

Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference.
J. Solid-State Circuits, 2019

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.
J. Solid-State Circuits, 2019

2018
Guest Editorial 2017 IEEE Custom Integrated Circuits Conference.
J. Solid-State Circuits, 2018

A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS.
J. Solid-State Circuits, 2017

A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.
J. Solid-State Circuits, 2017

A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.
J. Solid-State Circuits, 2017

Session 29 overview: Optical- and electrical-link innovations.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.
J. Solid-State Circuits, 2016

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.
J. Solid-State Circuits, 2016

CMOS ADC-based receivers for high-speed electrical and optical links.
IEEE Communications Magazine, 2016

2015
A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System.
IEEE Trans. on Circuits and Systems, 2015

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS.
J. Solid-State Circuits, 2015

A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique.
Proceedings of the Symposium on VLSI Circuits, 2015

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications.
J. Solid-State Circuits, 2014

An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning.
J. Solid-State Circuits, 2014

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS.
J. Solid-State Circuits, 2014

An Energy-Efficient Silicon Microring Resonator-Based Photonic Transmitter.
IEEE Design & Test, 2014

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A single parity check forward error correction method for high speed I/O.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures.
IEEE Trans. VLSI Syst., 2013

Sequential Correlated Level Shifting: A Switched-Capacitor Approach for High-Accuracy Systems.
IEEE Trans. on Circuits and Systems, 2013

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS.
J. Solid-State Circuits, 2013

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
J. Solid-State Circuits, 2013

A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier.
J. Solid-State Circuits, 2013

LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

High-speed wireline timing recovery & PLLs.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS.
IEEE Trans. on Circuits and Systems, 2012

A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter.
Microelectronics Journal, 2012

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
J. Solid-State Circuits, 2012

Digital-Assisted Asynchronous Compressive Sensing Front-End.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach.
IEEE Trans. on Circuits and Systems, 2011

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links.
J. Electrical and Computer Engineering, 2011

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Power Efficiency Comparisons of Interchip Optical Interconnect Architectures.
IEEE Trans. on Circuits and Systems, 2010

Optical I/O Technology for Tera-Scale Computing.
J. Solid-State Circuits, 2010

Optical technology for energy efficient I/O in high performance computing.
IEEE Communications Magazine, 2010

2009
Optical I/O technology for tera-scale computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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