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Ashish Singhadia

Orcid: 0000-0002-9122-4071

According to our database1, Ashish Singhadia authored at least 4 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Efficient HEVC Encoding to Meet Bitrate and PSNR Requirements Using Parametric Modeling.
[BibTeX]
[DOI]
Ashish Singhadia
,
Preeti Samhita Pati
,
Chetna Singhal
,
Indrajit Chakrabarti
Circuits Syst. Signal Process., 2022

2021
A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC.
[BibTeX]
[DOI]
Ashish Singhadia
,
Md. Minhazuddin
,
Meghan Mamillapalli
,
Indrajit Chakrabarti
Microprocess. Microsystems, September, 2021

2020
Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices.
[BibTeX]
[DOI]
Ashish Singhadia
,
Meghan Mamillapalli
,
Indrajit Chakrabarti
IEEE Trans. Consumer Electron., 2020

2019
A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC.
[BibTeX]
[DOI]
Ashish Singhadia
,
Pratik Bante
,
Indrajit Chakrabarti
IEEE Trans. Consumer Electron., 2019


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