Indrajit Chakrabarti

According to our database1, Indrajit Chakrabarti authored at least 70 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

VLSI Architecture for Enhanced Approximate Message Passing Algorithm.
IEEE Trans. Circuits Syst. Video Technol., 2020

Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices.
IEEE Trans. Consumer Electron., 2020

Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Hexagon Based Compressed Diamond Algorithm for motion estimation and its dedicated VLSI system for HD videos.
Expert Syst. Appl., 2020

A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC.
IEEE Trans. Consumer Electron., 2019

High-throughput Bit Flipping decoder for structured LDPC codes.
IET Commun., 2019

Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application.
CoRR, 2019

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip.
CoRR, 2019

Time-frequency masking based supervised speech enhancement framework using fuzzy deep belief network.
Appl. Soft Comput., 2019

Design and Implementation of Threshold Logic Functions Using Memristors.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

A Parallel Stochastic Number Generator With Bit Permutation Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm.
Microprocess. Microsystems, 2018

Design and evaluation of ZMesh topology for on-chip interconnection networks.
J. Parallel Distributed Comput., 2018

Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos.
Expert Syst. Appl., 2018

A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm.
Circuits Syst. Signal Process., 2018

Tensor-Train Long Short-Term Memory for Monaural Speech Enhancement.
CoRR, 2018

Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application.
CoRR, 2018

Another Look in the Analysis of Cooperative Spectrum Sensing over Nakagami-m Fading Channels.
IEEE Trans. Wirel. Commun., 2017

A novel framework for compressed sensing based scalable video coding.
Signal Process. Image Commun., 2017

FPGA Implementation of a Phase-Aware Single-Channel Speech Enhancement System.
Circuits Syst. Signal Process., 2017

Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of (512×512) Frames.
Circuits Syst. Signal Process., 2017

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Improving the Performance of Deep Learning Based Speech Enhancement System Using Fuzzy Restricted Boltzmann Machine.
Proceedings of the Pattern Recognition and Machine Intelligence, 2017

Efficient VLSI design of CAVLC decoder of H.264 for HD videos.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Runtime mitigation of illegal packet request attacks in Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Deep Recurrent Neural Network Based Monaural Speech Separation Using Recurrent Temporal Restricted Boltzmann Machines.
Proceedings of the Interspeech 2017, 2017

Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

Modelling of Cooperative Spectrum Sensing over Rayleigh Fading Without CSI in Cognitive Radio Networks.
Wirel. Pers. Commun., 2016

Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos.
Microprocess. Microsystems, 2016

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation.
J. Circuits Syst. Comput., 2016

Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal.
IET Signal Process., 2016

Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm.
IET Circuits Devices Syst., 2016

Low-Delay Parallel Architecture for Fractal Image Compression.
Circuits Syst. Signal Process., 2016

VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing.
CoRR, 2016

Two-Stage Temporal Processing for Single-Channel Speech Enhancement.
Proceedings of the Interspeech 2016, 2016

Hardware implementation of MIL-STD-1553 protocol over OFDMA-PHY based wireless high data rate avionics systems.
Proceedings of the 2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016

Motion Estimation for Video Coding - Efficient Algorithms and Architectures
Studies in Computational Intelligence 590, Springer, ISBN: 978-3-319-14376-7, 2015

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip.
Microprocess. Microsystems, 2015

Efficient architecture of adaptive rood pattern search technique for fast motion estimation.
Microprocess. Microsystems, 2015

High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter.
IET Circuits Devices Syst., 2015

High Performance VLSI Architecture for Three-Step Search Algorithm.
Circuits Syst. Signal Process., 2015

High Speed VLSI Architecture for 3-D Discrete Wavelet Transform.
CoRR, 2015

Hardware Implementation of Compressed Sensing based Low Complex Video Encoder.
CoRR, 2015

Automated detection and classification of mass from breast ultrasound images.
Proceedings of the 2015 Fifth National Conference on Computer Vision, 2015

Complexity assisted consistent quality rate control for high resolution H.264 video conferencing.
Proceedings of the 2015 Fifth National Conference on Computer Vision, 2015

Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems.
Proceedings of the Twenty First National Conference on Communications, 2015

ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

A phase-aware single channel speech enhancement technique using separate bayesian estimators for voiced and unvoiced regions with digital hearing aid application.
Proceedings of the 17th International Conference on E-health Networking, 2015

VLSI design of fast fractal image encoder.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Decentralized cooperative spectrum sensing in cognitive radio without fusion centre.
Proceedings of the Twentieth National Conference on Communications, 2014

High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder.
Proceedings of the Fourth National Conference on Computer Vision, 2013

Algorithm and architecture for quarter pixel motion estimation for H.264/AVC.
Proceedings of the Fourth National Conference on Computer Vision, 2013

Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver.
IET Commun., 2012

Power efficient motion estimation algorithm and architecture based on pixel truncation.
IEEE Trans. Consumer Electron., 2011

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation.
Int. J. Reconfigurable Comput., 2011

An improved low-power high-throughput log-MAP turbo decoder.
IEEE Trans. Consumer Electron., 2010

Low power VLSI architectures for one bit transformation based fast motion estimation.
IEEE Trans. Consumer Electron., 2010

Multi-standard programmable baseband modulator for next generation wireless communication
CoRR, 2010

Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code.
Proceedings of the Cellular Automata, 2010

A probabilistic adaptive algorithm for constructing hierarchical meshes.
IEEE Trans. Consumer Electron., 2009

High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000.
Proceedings of the Sixth Indian Conference on Computer Vision, Graphics & Image Processing, 2008

A Parallel Architecture for Successive Elimination Block Matching Algorithm.
Proceedings of the Sixth Indian Conference on Computer Vision, Graphics & Image Processing, 2008

An Improved Double Byte Error Correcting Code Using Cellular Automata.
Proceedings of the Cellular Automata, 2008