Ashkan Hosseinzadeh Namin

According to our database1, Ashkan Hosseinzadeh Namin authored at least 16 papers between 2006 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2013
Improved Area-Time Tradeoffs for Field Multiplication Using Optimal Normal Bases.
IEEE Trans. Computers, 2013

2012
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials.
IEEE Trans. Very Large Scale Integr. Syst., 2012

An Efficient Finite Field Multiplier Using Redundant Representation.
ACM Trans. Embed. Comput. Syst., 2012

High-Speed Architectures for Multiplication Using Reordered Normal Basis.
IEEE Trans. Computers, 2012

Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product.
IEEE Trans. Computers, 2012

2011
A Word-Level Finite Field Multiplier Using Normal Basis.
IEEE Trans. Computers, 2011

2010
High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis.
IET Circuits Devices Syst., 2010

Implementation of the compression function for selected SHA-3 candidates on FPGA.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009
A High-Speed Word Level Finite Field Multiplier in BBF<sub>2<sup>m</sup></sub> Using Redundant Representation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Efficient Hardware Implementation of the Hyperbolic Tangent Sigmoid Function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Artificial neural networks activation function HDL coder.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

High speed VLSI implementation of a finite field multiplier using redundant representation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A New Finite-Field Multiplier Using Redundant Representation.
IEEE Trans. Computers, 2008

A high speed word level finite field multiplier using reordered normal basis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Comb Architectures for Finite Field Multiplication in F(2^m).
IEEE Trans. Computers, 2007

2006
A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields.
Proceedings of the 13th IEEE International Conference on Electronics, 2006


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