Ashwani K. Rana

According to our database, Ashwani K. Rana authored at least 9 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell.

Shelja Kaushal, Ashwani K. Rana

Integr., 2023

2022

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET.

Shelja Kaushal, Ashwani K. Rana

Microelectron. J., 2022

2018

Evaluation of statistical variability and parametric sensitivity of non-uniformly doped Junctionless FinFET.

Shalu Kaundal, Ashwani K. Rana

Microelectron. Reliab., 2018

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET.

Rajneesh Sharma, Rituraj S. Rathore, Ashwani K. Rana

J. Circuits Syst. Comput., 2018

2016

Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs.

Rituraj Singh Rathore, Rajneesh Sharma, Ashwani K. Rana

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015

Strained Si: Opportunities and challenges in nanoscale MOSFET.

Rajneesh Sharma, Ashwani K. Rana

Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014

DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic.

Amita Nandal, T. Vigneswaran, Ashwani K. Rana

Circuits Syst. Signal Process., 2014

2011

Modeling gate Current for nano Scale MOSFET with Different gate spacer.

Ashwani K. Rana, Narottam Chand, Vinod Kapoor

J. Circuits Syst. Comput., 2011

Performance evaluation of FD-SOI Mosfets for different metal gate work function

Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav, Devendra Giri

CoRR, 2011