Aurelio Morales-Villanueva

According to our database, Aurelio Morales-Villanueva authored at least 6 papers between 2013 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Development of a Digital Twin Model for a Hydrogen Production Plant Based on Artificial Intelligence Techniques.

Rubén Aquize Palacios, Juan Moises Maurício Villanueva, Aurelio Morales-Villanueva, Cesar Briceño Aranda, Oswaldo A. Waters Torres, James Erick Vílchez García, Roberto M. Dioses Soriano, Eduardo Roberto Rodriguez

IEEE Access, 2026

2024

Uncertainty Evaluation of a Gas Turbine Model Based on a Nonlinear Autoregressive Exogenous Model and Monte Carlo Dropout.

Armando Cajahuaringa, Rubén Aquize Palacios, Juan Moises Maurício Villanueva, Aurelio Morales-Villanueva, José A. D. Machuca, Juan Contreras, Kiara Rodríguez Bautista

Sensors, January, 2024

2016

Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs.

Aurelio Morales-Villanueva, Rohit Kumar, Ann Gordon-Ross

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs.

Aurelio Morales-Villanueva, Ann Gordon-Ross

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2013

On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs.

Aurelio Morales-Villanueva, Ann Gordon-Ross

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs.

Aurelio Morales-Villanueva, Ann Gordon-Ross

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013