Avinash Ananthakrishnan

According to our database, Avinash Ananthakrishnan authored at least 3 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Power management on 14 nm Intel® Core- M processor.

Anant Deval, Avinash Ananthakrishnan, Craig Forbell

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2012

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge.

Efraim Rotem, Alon Naveh, Avinash Ananthakrishnan, Eliezer Weissmann, Doron Rajwan

IEEE Micro, 2012

2011

Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge.

Efi Rotem, Alon Naveh, Doron Rajwan, Avinash Ananthakrishnan, Eliezer Weissmann

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011