Avishay Maman

According to our database1, Avishay Maman authored at least 2 papers between 2004 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2006
Reusable On-Chip System Level Verification for Simulation Emulation and Silicon.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2004
Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004


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