Aynaz Vatankhahghadim

According to our database1, Aynaz Vatankhahghadim authored at least 4 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2015
A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014


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