Safeen Huda

According to our database, Safeen Huda authored at least 16 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer.

Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini

Proceedings of the 21st USENIX Symposium on Networked Systems Design and Implementation, 2024

2022

Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers.

Paras Jain, Safeen Huda, Martin Maas, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A full-stack search technique for domain optimized deep learning accelerators.

Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Kartik Prabhu, Quoc V. Le, Anna Goldie, Azalia Mirhoseini

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

A Full-stack Accelerator Search Technique for Vision Applications.

Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Quoc V. Le, Anna Goldie, Azalia Mirhoseini

CoRR, 2021

2020

Optimizing FPGA Logic Block Architectures for Arithmetic.

Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz

IEEE Trans. Very Large Scale Integr. Syst., 2020

2017

Leveraging Unused Resources for Energy Optimization of FPGA Interconnect.

Safeen Huda, Jason Helge Anderson

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Hybrid LUT/Multiplexer FPGA Logic Architectures.

S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson

IEEE Trans. Very Large Scale Integr. Syst., 2016

Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques.

Safeen Huda, Jason Helge Anderson

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Towards PVT-Tolerant Glitch-Free Operation in FPGAs.

Safeen Huda, Jason Helge Anderson

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2014

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions.

Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Optimizing effective interconnect capacitance for FPGA power reduction.

Safeen Huda, Jason Helge Anderson, Hirotaka Tamura

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

On Hard Adders and Carry Chains in FPGAs.

Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

A Novel STT-MRAM Cell With Disturbance-Free Read Operation.

Safeen Huda, Ali Sheikholeslami

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Charge recycling for power reduction in FPGA interconnect.

Safeen Huda, Jason Helge Anderson, Hirotaka Tamura

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2010

Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS.

David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Clock gating architectures for FPGA power reduction.

Safeen Huda, Muntasir Mallick, Jason Helge Anderson

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009