B. B. Shabarinath

According to our database, B. B. Shabarinath authored at least 6 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2025

Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference.

B. B. Shabarinath, Muralidhar Pullakandam

IEEE Access, 2025

2023

SoC-based real-time SVM classification with integrated training using HLS and PYNQ.

B. B. Shabarinath, Muralidhar Pullakandam

Microprocess. Microsystems, 2023

PYNQ Overlay for SVM-based Melanoma Classification with Learning Ability.

B. B. Shabarinath, Bore Sathwik Vamshi, Rudrangi Manjunath, P. Suraj Reddy, P. Muralidhar

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022

Epileptic Seizure Inference using Kernalized SVM with integrated training on PYNQ Z2.

B. B. Shabarinath, P. Muralidhar

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020

Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm.

B. B. Shabarinath, P. Muralidhar

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Convolutional Neural Network based Traffic-Sign Classifier Optimized for Edge Inference.

B. B. Shabarinath, P. Muralidhar

Proceedings of the 2020 IEEE Region 10 Conference, 2020