B. B. Shabarinath

Orcid: 0000-0001-6664-208X

According to our database1, B. B. Shabarinath authored at least 7 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of six.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Scalable SoC Architecture for Parallel-Pixel Classification of Hyperspectral Images Using Weighted-Summation Kernel SVM.
Concurr. Comput. Pract. Exp., February, 2026

2025
Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference.
IEEE Access, 2025

2023
SoC-based real-time SVM classification with integrated training using HLS and PYNQ.
Microprocess. Microsystems, 2023

PYNQ Overlay for SVM-based Melanoma Classification with Learning Ability.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022
Epileptic Seizure Inference using Kernalized SVM with integrated training on PYNQ Z2.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020
Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Convolutional Neural Network based Traffic-Sign Classifier Optimized for Edge Inference.
Proceedings of the 2020 IEEE Region 10 Conference, 2020


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