Muralidhar Pullakandam

Orcid: 0000-0002-3288-9989

According to our database1, Muralidhar Pullakandam authored at least 9 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device.
Des. Autom. Embed. Syst., September, 2023

SoC-based real-time SVM classification with integrated training using HLS and PYNQ.
Microprocess. Microsystems, 2023

Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

The chaotic-based challenge feed mechanism for Arbiter Physical Unclonable Functions (APUFs) with enhanced reliability in IoT security.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Efficient successive cancellation decoder architecture for multi-kernel polar codes.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security.
Microprocess. Microsystems, November, 2021

ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security.
Proceedings of the Internet of Things. Technology and Applications, 2021


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