Bastian Koppelmann

According to our database, Bastian Koppelmann authored at least 5 papers between 2014 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.

Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

2020

A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.

Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt

Proceedings of the 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2020

2019

RISC-V Extensions for Bit Manipulation Instructions.

Bastian Koppelmann, Peer Adelt, Wolfgang Mueller, Christoph Scheytt

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2016

Fast dynamic fault injection for virtual microcontroller platforms.

Peer Adelt, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, Christoph Scheytt

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

2014

Portierung der TriCore-Architektur auf QEMU.

Bastian Koppelmann, Markus Becker, Wolfgang Müller

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014