Bayartulga Ishdorj

According to our database, Bayartulga Ishdorj authored at least 6 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2026

Reliability-Enhanced Offset-Canceling Current-Sampling Sense Amplifier for 2T-2MTJ MRAM PUF.

Mingu Han, Jaehwan Kim, Bayartulga Ishdorj, Jaeyong Jang, Taehui Na

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2026

Recovery-Signal-Based Low-Cost Quadruple-Node-Upset-Tolerant and Self-Recoverable Latch Design for Aerospace Applications.

Jaeyong Jang, Bayartulga Ishdorj, Urmila Saha, Taehui Na

IEEE Trans. Aerosp. Electron. Syst., 2026

2025

Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM.

Jaehwan Kim, Mingu Han, Bayartulga Ishdorj, Taehui Na

IEEE Trans. Circuits Syst. II Express Briefs, May, 2025

Double-Node-Upset Fully-Tolerant/Recoverable and Triple-Node-Upset Partially-Tolerant Self-Recoverable Latch Design for Aerospace Applications.

Urmila Saha, Bayartulga Ishdorj, Jaeyong Jang, Taehui Na

IEEE Access, 2025

2023

Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile Flip-Flop Designs in the Subthreshold Voltage Region.

Bayartulga Ishdorj, Taehui Na

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques.

Bayartulga Ishdorj, Doyeon Kim, Seongmin Ahn, Taehui Na

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023