Jaeyong Jang
Orcid: 0009-0005-4482-2545
According to our database1,
Jaeyong Jang authored at least 7 papers
between 2023 and 2026.
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Bibliography
2026
Reliability-Enhanced Offset-Canceling Current-Sampling Sense Amplifier for 2T-2MTJ MRAM PUF.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2026
Recovery-Signal-Based Low-Cost Quadruple-Node-Upset-Tolerant and Self-Recoverable Latch Design for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2026
2025
Double-Node-Upset Fully-Tolerant/Recoverable and Triple-Node-Upset Partially-Tolerant Self-Recoverable Latch Design for Aerospace Applications.
IEEE Access, 2025
An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention Time.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic.
Proceedings of the Eleventh International Conference on Learning Representations, 2023