Benjamín Sahelices

Orcid: 0000-0002-3380-3403

According to our database1, Benjamín Sahelices authored at least 13 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Interpretability of deep learning models in analysis of Spanish financial text.
Neural Comput. Appl., May, 2024

2023
Correction to: Systematic Review of Machine Learning Applied to the Prediction of Obesity and Overweight.
J. Medical Syst., December, 2023

Systematic Review of Machine Learning applied to the Prediction of Obesity and Overweight.
J. Medical Syst., 2023

2022
Board of Directors' Profile: A Case for Deep Learning as a Valid Methodology to Finance Research.
Int. J. Interact. Multim. Artif. Intell., 2022

Depression Classification From Tweets Using Small Deep Transfer Learning Language Models.
IEEE Access, 2022

2014
OmniOrder: Directory-based conflict serialization of transactions.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocol.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Volition: scalable and precise sequential consistency violation detection.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.
J. Comput. Sci. Technol., 2012

BulkSMT: Designing SMT processors for atomic-block execution.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2009
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009


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