According to our database1, Víctor Viñals authored at least 59 papers between 1996 and 2019.
Legend:Book In proceedings Article PhD thesis Other
A fault-tolerant last level cache for CMPs operating at ultra-low voltage.
J. Parallel Distrib. Comput., 2019
ReD: A reuse detector for content selection in exclusive shared last-level caches.
J. Parallel Distrib. Comput., 2019
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
Proceedings of the Workshop on Computer Architecture Education, 2019
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
Proceedings of the Data Compression Conference, 2019
Reuse Detector: Improving the Management of STT-RAM SLLCs.
Comput. J., 2018
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
IEEE Trans. VLSI Syst., 2017
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors.
Microprocessors and Microsystems - Embedded Hardware Design, 2016
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
J. Parallel Distrib. Comput., 2016
ACDC: Small, Predictable and High-Performance Data Cache.
ACM Trans. Embedded Comput. Syst., 2015
A predictable hardware to exploit temporal reuse in real-time and embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2015
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.
Capturing the sensitivity of optical network quality metrics to its network interface parameters.
Concurrency and Computation: Practice and Experience, 2014
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Exploiting reuse locality on inclusive shared last-level caches.
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems.
Journal of Systems Architecture - Embedded Systems Design, 2013
The reuse cache: downsizing the shared last-level cache.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.
IEEE Trans. VLSI Syst., 2012
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.
J. Comput. Sci. Technol., 2012
A Small and Effective Data Cache for Real-Time Multitasking Systems.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012
Filtering directory lookups in CMPs.
Microprocessors and Microsystems - Embedded Hardware Design, 2011
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems.
Journal of Systems Architecture - Embedded Systems Design, 2011
Multi-level Adaptive Prefetching based on Performance Gradient Tracking.
J. Instruction-Level Parallelism, 2011
Filtering Directory Lookups in CMPs with Write-Through Caches.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010
Store Buffer Design for Multibanked Data Caches.
IEEE Trans. Computers, 2009
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
Light NUCA: A proposal for bridging the inter-cache latency gap.
Proceedings of the Design, Automation and Test in Europe, 2009
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008
Avoiding the WCET Overestimation on LRU Instruction Cache.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008
Low-Cost Adaptive Data Prefetching.
Proceedings of the Euro-Par 2008, 2008
Data prefetching in a cache hierarchy with high bandwidth and capacity.
SIGARCH Computer Architecture News, 2007
A proposal to introduce power and energy notions in computer architecture laboratories.
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007
Microarchitectural Support for Speculative Register Renaming.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Software Demand, Hardware Supply.
IEEE Micro, 2006
Speeding-Up Synchronizations in DSM Multiprocessors.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Speculative early register release.
Proceedings of the Third Conference on Computing Frontiers, 2006
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors.
Hardware support for early register release.
Store Buffer Design in First-Level Multibanked Data Caches.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Late Allocation and Early Release of Physical Registers.
IEEE Trans. Computers, 2004
Contents Management in First-Level Multibanked Data Caches.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
Counteracting Bank Misprediction in Sliced First-Level Caches.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
Hardware Schemes for Early Register Release.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001
Dynamic Register Renaming Through Virtual-Physical Registers.
J. Instruction-Level Parallelism, 2000
Modeling load address behaviour through recurrences.
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000
Delaying Physical Register Allocation through Virtual-Physical Registers.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Characterization and Improvement of Load/Store Cache-based Prefetching.
Proceedings of the 12th international conference on Supercomputing, 1998
Performance Assessment of Contents Management in Multilevel On-Chip Caches.
Proceedings of the 22rd EUROMICRO Conference '96, 1996