According to our database1, Víctor Viñals authored at least 60 papers between 1996 and 2020.
Legend:Book In proceedings Article PhD thesis Other
IEEE ACM Trans. Comput. Biol. Bioinform., 2020
J. Parallel Distributed Comput., 2019
J. Parallel Distributed Comput., 2019
Proceedings of the Workshop on Computer Architecture Education, 2019
Proceedings of the Data Compression Conference, 2019
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Microprocess. Microsystems, 2016
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
J. Parallel Distributed Comput., 2016
ACM Trans. Embed. Comput. Syst., 2015
J. Syst. Archit., 2015
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.
ACM Trans. Archit. Code Optim., 2014
Capturing the sensitivity of optical network quality metrics to its network interface parameters.
Concurr. Comput. Pract. Exp., 2014
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
ACM Trans. Archit. Code Optim., 2013
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems.
J. Syst. Archit., 2013
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
IEEE Trans. Very Large Scale Integr. Syst., 2012
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
ACM Trans. Archit. Code Optim., 2012
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.
J. Comput. Sci. Technol., 2012
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems.
J. Syst. Archit., 2011
J. Instr. Level Parallelism, 2011
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008
SIGARCH Comput. Archit. News, 2007
A proposal to introduce power and energy notions in computer architecture laboratories.
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Proceedings of the Third Conference on Computing Frontiers, 2006
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors.
ACM Trans. Archit. Code Optim., 2005
Int. J. High Perform. Comput. Netw., 2005
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001
J. Instr. Level Parallelism, 2000
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Proceedings of the 12th international conference on Supercomputing, 1998
Proceedings of the 22rd EUROMICRO Conference '96, 1996