Bhavana S

According to our database, Bhavana S authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2026

OK-BMM: A Power-Performance-Efficient Overlap-Free Karatsuba Based Barrett Modular Multiplier for Secure Embedded Systems.

Bhavana S, B. Keerthana, Madhav Rao

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

Mixed-Precision Booth Factored Systolic Array Design for Accelerating Neural Networks.

Sneha Dandekar, Bhavana S, Madhav Rao

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

R-BMM: A Reconfigurable Barrett Modular Multiplier Architecture for High-Performance Cryptographic Systems.

Keerthana B, Bhavana S, Madhav Rao

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

2025

Hardware Efficient Multiplier Design Using an Optimal Mix of Approximate Booth Encodings.

Chandan Kumar N. S, Bhavana S, Ajitesh Kumar Singh, Madhav Rao

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025