Bi Wu

Orcid: 0000-0001-9972-0478

According to our database1, Bi Wu authored at least 56 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications.
IEEE Trans. Computers, February, 2024

2023
Fault Diagnosis of Multi-Railway High-Speed Train Bogies by Improved Federated Learning.
IEEE Trans. Veh. Technol., June, 2023

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Weighted-leader search: A new choice in metaheuristic and its application in real-world large-scale optimization.
Adv. Eng. Softw., February, 2023

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs.
IEEE Trans. Emerg. Top. Comput., 2023

A Survey of MRAM-Centric Computing: From Near Memory to In Memory.
IEEE Trans. Emerg. Top. Comput., 2023

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
High-Accuracy and Adaptive Fault Diagnosis of High-Speed Train Bogie Using Dense-Squeeze Network.
IEEE Trans. Veh. Technol., 2022

Stepwise Adaptive Convolutional Network for Fault Diagnosis of High-Speed Train Bogie Under Variant Running Speeds.
IEEE Trans. Ind. Informatics, 2022

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Progress and Prospects of Quantum Algorithms.
Proceedings of the 4th World Symposium on Software Engineering, 2022

Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Low-cost stochastic number generator based on MRAM for stochastic computing.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

A High-Speed CNN Hardware Accelerator with Regular Pruning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A NAND-SPIN-Based Magnetic ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

LeanNet: An Efficient Convolutional Neural Network for Digital Number Recognition in Industrial Products.
Sensors, 2021

Failure Intelligent Data Analysis Research of Last Stage Blades of Feedwater Pump Turbine in a Power Plant.
Proceedings of the 3rd International Conference on Artificial Intelligence and Advanced Manufacture, 2021

2020
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories.
IEEE Trans. Circuits Syst., 2020

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.
ACM J. Emerg. Technol. Comput. Syst., 2020

A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion.
ACM J. Emerg. Technol. Comput. Syst., 2020

2019
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices.
CoRR, 2019

2018
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Event Detection Method for Social Networks Based on Evolution Fluctuations of Nodes.
IEEE Access, 2018

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Optical Flow Based Face Hallucination Via Weightedly-Constrained Representation.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Extreme Learning Machine Based on Evolutionary Multi-objective Optimization.
Proceedings of the Bio-inspired Computing: Theories and Applications, 2017

2016
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliab., 2016

PDS: pseudo-differential sensing scheme for STT-MRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Locally Weighted Learning: How and When Does it Work in Bayesian Networks?
Int. J. Comput. Intell. Syst., 2015

Government factors that influence the relevance between environmental and economic growth.
Ann. Oper. Res., 2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2014
SpanDex: Secure Password Tracking for Android.
Proceedings of the 23rd USENIX Security Symposium, San Diego, CA, USA, August 20-22, 2014., 2014

2013
Virtualization with Limited Hardware Support.
PhD thesis, 2013

2012
Block storage virtualization with commodity secure digital cards.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012

2011
CrowdLab: An architecture for volunteer mobile testbeds.
Proceedings of the Third International Conference on Communication Systems and Networks, 2011

2010
A Qualitative Study on the Value of Governmental Economic Service.
J. Comput., 2010

2007
Design and control of a modular actuator driven humanoid robot.
Proceedings of the 2007 7th IEEE-RAS International Conference on Humanoid Robots, November 29th, 2007

Locomotion planning and implementation of humanoid robot Robo-Eectus Senior (RESr-1).
Proceedings of the 2007 7th IEEE-RAS International Conference on Humanoid Robots, November 29th, 2007


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