Bing-Chen Wu
Orcid: 0000-0002-7451-4261Affiliations:
- Chang-Gung University, Taiwan
According to our database1,
Bing-Chen Wu
authored at least 12 papers
between 2014 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
SOP<sup>2</sup>: Transfer Learning with Scene-Oriented Prompt Pool on 3D Object Detection.
Proceedings of the IEEE International Conference on Advanced Visual and Signal-Based Systems, 2025
2023
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS.
IEEE J. Solid State Circuits, November, 2023
2022
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
IEEE Trans. Circuits Syst., 2020
2019
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2018
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
J. Low Power Electron., 2018
2015
2014
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design.
Microelectron. J., 2014