Tsung-Te Liu
Orcid: 0000-0002-5433-9830
According to our database1,
Tsung-Te Liu
authored at least 40 papers
between 2004 and 2023.
Collaborative distances:
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Bibliography
2023
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS.
IEEE J. Solid State Circuits, November, 2023
A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing.
IEEE J. Solid State Circuits, May, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models.
Proceedings of the IEEE Automatic Speech Recognition and Understanding Workshop, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
J. Electron. Test., 2021
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst., 2020
IEEE J. Solid State Circuits, 2020
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2018
J. Low Power Electron., 2018
2017
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2015
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction.
Proceedings of the VLSI Design, Automation and Test, 2015
2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression.
IEEE J. Solid State Circuits, 2013
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
2007
2004
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004