Bingjing Hou
Orcid: 0009-0009-2560-9721
According to our database1,
Bingjing Hou
authored at least 2 papers
between 2024 and 2025.
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Bibliography
2025
A Multiplier-Balanced and Area-Efficient Architecture for Low-Frequency Non-Separable Secondary Transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
A High-Throughput and Memory-Efficient Deblocking Filter Hardware Architecture for VVC.
IEEE Trans. Circuits Syst. Video Technol., December, 2024