Yibo Fan

According to our database1, Yibo Fan authored at least 49 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2019
Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video\/Image-Based Virtual-Reality Scenes.
IEEE Consumer Electronics Magazine, 2019

2018
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation.
IEEE Trans. Circuits Syst. Video Techn., 2018

Parallelized Contour Based Depth Map Coding in DIBR.
Proceedings of the Advances in Multimedia Information Processing - PCM 2018, 2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.
Proceedings of the International SoC Design Conference, 2018

An Automatic Task Partition Method for Multi-core System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Q Value-Based Dynamic Programming with Boltzmann Distribution by Using Neural Network.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Content adaptive tiling method based on user access preference for streaming panoramic video.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

2017
A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding.
IEICE Transactions, 2017

An efficient spherical video sampling scheme based on Cube model.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

2016
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC.
IEEE Trans. Multimedia, 2016

A highly sensitive wide-range weak current detection circuit for implantable glucose monitoring.
IEICE Electronic Express, 2016

Quarter LCU based integer motion estimation algorithm for HEVC.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding.
IEEE Trans. Circuits Syst. Video Techn., 2015

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs.
IEEE Trans. on Circuits and Systems, 2015

A high-efficiency rectifier for passive UHF RFID with wide incident power range.
IEICE Electronic Express, 2015

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Iterative disparity voting based stereo matching algorithm and its hardware implementation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A flexible HEVC intra mode decision hardware for 8kx4k real time encoder.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT.
IEEE Trans. VLSI Syst., 2014

A hardware-friendly method for rate-distortion optimization of HEVC intra coding.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Transactions, 2013

A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design.
IEICE Transactions, 2013

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC.
IEICE Electronic Express, 2013

A high-throughput VLSI architecture for deblocking filter in HEVC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A fast 8×8 IDCT algorithm for HEVC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications.
IEICE Transactions, 2012

An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder.
IEICE Transactions, 2012

A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder.
Proceedings of the Advances in Multimedia Modeling - 18th International Conference, 2012

A parallel CAVLC design for 4096×2160p encoder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC.
IEICE Transactions, 2011

A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder.
IEICE Electronic Express, 2011

MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A two-way parallel CAVLC encoder for 4K×2K H.264/AVC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A hardware/software co-design approach for multiple-standard video bitstream parsing.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008
An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard.
IEICE Transactions, 2008

Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm.
IEICE Transactions, 2008

A High-Speed Design of Montgomery Multiplier.
IEICE Transactions, 2008

2007
A New Video Encryption Scheme for H.264/AVC.
Proceedings of the Advances in Multimedia Information Processing, 2007

2006
A modified high-radix scalable Montgomery multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A high-performance platform-based SoC for information security.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture.
Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005


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