Ming-e Jing

According to our database1, Ming-e Jing authored at least 19 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.
Proceedings of the International SoC Design Conference, 2018

An Automatic Task Partition Method for Multi-core System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2014
A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. on Circuits and Systems, 2014

2013
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Time-Division-Multiplexer based routing algorithm for NoC system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Implementation and optimization of 3780-point FFT on multi-core system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Efficient implementation of 3780-point FFT on a 16-core processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Task-binding based branch-and-bound algorithm for NoC mapping.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Analog layout retargeting with geometric programming and constrains symbolization method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A method of quadratic programming for mapping on NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A Folding Strategy for SAT solvers based on Shannon's expansion theorem.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2007
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Solving SAT problem by heuristic polarity decision-making algorithm.
Science in China Series F: Information Sciences, 2007

2005
Efficient parametric yield optimization of VLSI circuit by uniform design sampling method.
Microelectronics Reliability, 2005


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