Bobin Deng
Orcid: 0000-0001-8361-9025
According to our database1,
Bobin Deng
authored at least 27 papers
between 2011 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
The Robustness of Spiking Neural Networks in Federated Learning with Compression Against Non-omniscient Byzantine Attacks.
CoRR, January, 2025
A Sparsity Predicting Approach for Large Language Models via Activation Pattern Clustering.
Proceedings of the Euro-Par 2025: Parallel Processing, 2025
2024
ACM Trans. Archit. Code Optim., September, 2024
The Robustness of Spiking Neural Networks in Communication and its Application towards Network Efficiency in Federated Learning.
Proceedings of the IEEE International Performance, 2024
Characterizing and Understanding the Performance of Small Language Models on Edge Devices.
Proceedings of the IEEE International Performance, 2024
Proceedings of the IEEE International Performance, 2024
Predicting Protein-Protein Binding Affinity with Deep Learning: A Comparative Analysis of CNN and Transformer Models.
Proceedings of the 36th IEEE International Conference on Tools with Artificial Intelligence, 2024
Practical Considerations of Fully Homomorphic Encryption in Privacy-Preserving Machine Learning.
Proceedings of the IEEE International Conference on Big Data, 2024
Building a Resilient and Sustainable Grid: A Study of Challenges and Opportunities in AI for Smart Virtual Power Plants.
Proceedings of the 2024 ACM Southeast Conference, 2024
Proceedings of the 2024 ACM Southeast Conference, 2024
An Empirical Analysis and Resource Footprint Study of Deploying Large Language Models on Edge Devices.
Proceedings of the 2024 ACM Southeast Conference, 2024
2023
Proceedings of the 12th International Conference on Networks, Communication and Computing, 2023
Deep Machine Learning on Segmenting and Classifying Crop Images Taken by Unmanned Aerial Vehicle.
Proceedings of the IEEE International Conference on Big Data, 2023
2022
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.
IEEE Trans. Computers, 2022
2021
PhD thesis, 2021
2018
ACM Trans. Archit. Code Optim., 2018
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2014
Efficient execution of speculative threads and transactions with hardware transactional memory.
Future Gener. Comput. Syst., 2014
2012
Int. J. Inf. Technol. Commun. Convergence, 2012
Proceedings of the International Conference on Supercomputing, 2012
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor.
Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012
2011
A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011